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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
PRELIMINARY
Some of contents are described for general products and are subject to change without notice.
DESCRIPTION
M2V64S20BTP is organized as 4-bank x4,194,304-word x 4-bit,and M2V64S30BTP is organized as 4-bank x 2097152-word x 8-bit ,and M2V64S40BTP is organized as 4-bank x 1048576-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M2V64S20BTP,M2V64S30BTP,M2V64S40BTP achieves very high speed data rates up to 133MHz, and is suitable for main memory or graphic memory in computer systems.
FEATURES
ITEM tCLK tRAS tRCD tAC tRC Icc1 Icc6 Clock Cycle Time (Min.) (Min.) (Min.) (Max.) (CL=3) (Min.) M2V64S20TP M2V64S30TP M2V64S40TP -6 7.5ns 45ns 20.0ns 5.4ns 67.5ns 120mA (Max.) 1mA
Active to Precharge Command Period Row to Column Delay Access Time from CLK Ref/Active Command Period Operation Current (Max.) [Single Bank] Self Refresh Current
- Single 3.3V 0.3V power supply - Max. Clock frequency -6 : 133MHz [PC133<3-3-3> ] - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0,BA1(Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Random column access - Auto precharge / All bank precharge controlled by A10 - Auto and self refresh - 4096 refresh cycles /64ms - LVTTL Interface - Package 400-mil, 54-pin Thin Small Outline (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
PIN CONFIGURATION (TOP VIEW) M2V64S20BTP M2V64S30BTP M2V64S40BTP
Vdd NC VddQ NC DQ0 VssQ NC NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 Vdd Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 Vdd Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10 A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss
CLK CKE /CS /RAS /CAS /WE DQ0-3(x4), DQ0-7(x8), DQ0-15(x16) DQM (x4, x8) ,DQML/U (x16) A0-11 BA0,1 Vdd VddQ Vss VssQ
: Master Clock : Clock Enable : Chip Select : Row Address Strobe : Column Address Strobe : Write Enable : Data I/O : Output Disable/ Write Mask : Address Input : Bank Address : Power Supply : Power Supply for Output : Ground : Ground for Output
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
BLOCK DIAGRAM
DQ0-3 (x4) DQ0-7 (x8) DQ0-15 (x16)
I/O Buffer
Memory Array Memory Array Memory Array Memory Array Bank #0 Bank #1 Bank #2 Bank #3
Mode Register Control Circuitry
Address Buffer Clock Buffer
Control Signal Buffer
A0-11 BA0,1
/CS /RAS /CAS /WE DQM
CLK
CKE
Type Designation Code
This rule is applied only to Synchronous DRAM families beyond 64M B-version.
M2 V 64 S 2 0 B TP - 7
Access Item Package Type TP: TSOP(II) Process Generation Function 0: Random Column Organization 2n 2: x4, 3: x8, 4: x16 Synchronous DRAM Density 64:64M bits Interface S: SSTL, V:LVTTL Mitsubishi Semiconductor Memory
MITSUBISHI ELECTRIC
3
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
PIN FUNCTION
CLK Input Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. /CS /RAS, /CAS, /WE Input Input Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-A9(x4), A0-A8(x8), A0-7(x16) . A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data In and Data out are referenced to the rising edge of CLK.
CKE
Input
A0-11
Input
BA0,1 DQ0-3(x4), DQ0-7(x8), DQ0-15(x16) DQM(x4,x8), DQMU/L(x16) Vdd, Vss VddQ, VssQ
Input
Input / Output
Input
Din Mask / Output Disable: When DQMU/L is high in burst write, Din for the current cycle is masked. When DQMU/L is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry. VddQ and VssQ are supplied to the Output Buffers only.
Power Supply Power Supply
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
BASIC FUNCTIONS
The M2V64S20(30,40)BTP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.
CLK /CS /RAS /CAS /WE CKE A10
Chip Select : L=select, H=deselect Command Command Command Refresh Option @refresh command Precharge Option @precharge or read/write command define basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge,READA). Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, both banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated inter-nally. After this command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with AutoPrecharge Column Address Entry & Read Column Address Entry & Read with AutoPrecharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set READA REFA REFS REFSX TBST MRS H H H L L H H X H L H H X X L L L H L L L H L L X H H L L L L X H H L H H H X H L L V X X X X X L X X X X X X L H X X X X X L V X X X X X V*1 READ H X L H L H V X L V MNEMONIC DESEL NOP ACT PRE PREA WRITE CKE n-1 H H H H H H CKE n X X X X X X /CS H L L L L L /RAS X H L L L H /CAS X H H H H L /WE X H H L L L BA0,1 X X V V X V A11 X X V X X X A10 X X V L H L A0-9 X X V X X V
WRITEA
H
X
L
H
L
L
V
X
H
V
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
FUNCTION TRUTH TABLE
Current State IDLE /CS H L L L L L L L ROW ACTIVE H L L L L L L L L READ H L L L /RAS X H H H L L L L X H H H H L L L L X H H H /CAS X H H L H H L L X H H L L H H L L X H H L /WE X H L X H L H L X H L H L H L H L X H L H X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 Address Command DESEL NOP TBST NOP NOP ILLEGAL*2 Action
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
WRITE / WRITEA ACT PRE / PREA REFA MRS
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
FUNCTION TRUTH TABLE (continued)
Current State WRITE /CS H L L L /RAS X H H H /CAS X H H L /WE X H L H X X BA BA, CA, A10 Address Command DESEL NOP TBST Action NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge*3 WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
8
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
FUNCTION TRUTH TABLE (continued)
Current State PRE CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS X H H H L L L L X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP NOP ILLEGAL*2
READ / WRITE ILLEGAL*2 ACT PRE / PREA REFA MRS ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
FUNCTION TRUTH TABLE (continued)
Current State REFRESHING /CS H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS X H H H L L L L X H H H L L L L /CAS X H H L H H L L X H H L H H L L /WE X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TBST Action NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TBST ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
MITSUBISHI ELECTRIC
10
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle*3 Exit CLK Suspend at Next Cycle*3 Maintain CLK Suspend Action
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
SIMPLIFIED STATE DIAGRAM
SELF REFRESH
REFS REFSX
MODE REGISTER SET
MRS
IDLE
REFA
AUTO REFRESH
CKEL
CLK SUSPEND
CKEH ACT CKEL
POWER DOWN
CKEH TBST (for Full Page)
ROW ACTIVE
TBST (for Full Page)
WRITE WRITEA READA READ WRITE
READ
WRITE SUSPEND
CKEL
CKEL
WRITE
CKEH
READ
CKEH
READ SUSPEND
WRITEA WRITEA READA
READA
WRITEA SUSPEND
CKEL
CKEL
WRITEA
CKEH PRE
PRE PRE
READA
CKEH
READA SUSPEND
POWER APPLIED
POWER ON
PRE
PRE CHARGE Automatic Sequence Command Sequence
MITSUBISHI ELECTRIC
12
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1.Clock will be applied at power up along with power. Attempt to maintain CKE high, DQM (x4,x8), DQMU/L (x16) high and NOP condition at the inputs along with power. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200us. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
BA0 BA1 A11 A10 A9 0 0 0 0 WM A8 0 A7 0 A6 A5 A4 A3 BT A2 A1 BL CLK /CS /RAS /CAS /WE BA0,1 A11-A0 A0
V
LTMODE
CL 000 001 LATENCY MODE 010 011 100 101 110 111 0 1
/CAS LATENCY R R 2 3 R R R R BURST SINGLE BIT BURST LENGTH
BL 000 001 010 011 100 101 110 111 BURST TYPE 0 1
BT= 0 1 2 4 8 R R R FP SEQUENTIAL INTERLEAVE
BT= 1 1 2 4 8 R R R R
WRITE MODE
R: Reserved for Future Use FP: Full Page
MITSUBISHI ELECTRIC
13
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
[ /CAS LATENCY ] /CAS latency, CL, is used to synchronize the first output data with the CLK frequency, i.e., the speed of CLK determines which CL should be used. First output data is available after CL cycles from READ command.
/CAS Latency Timing(BL=4)
CLK Command
ACT tRCD
READ
Address
X
Y CL=2
DQ DQ
Q0
Q1
Q2
Q3
CL=2
Q3
CL=3
Q0
Q1
Q2
CL=3
[ BURST LENGTH ] The burst length, BL, determines the number of consecutive writes or reads that will be automatically performed after the initial write or read command. For BL=1,2,4,8, full page the output data is tristated (Hi-Z) after the last read. For BL=FP (Full Page), the TBST (Burst Terminate) command should be issued to stop the output of data.
Burst Length Timing( CL=2 )
tRCD CLK
Command
ACT
READ
Address DQ DQ DQ DQ DQ
X
Y Q0 Q0 Q0 Q0 Q0 Q1 Q1 Q1 Q1 Q2 Q2 Q2 Q3 Q3 Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 Q7 Q8 Qm Q0 Q1 BL=1 BL=2 BL=4 BL=8 BL=FP
M2V64S20B : m=1023 M2V64S30B : m=511 M2V64S40B : m=255
Full Page counter rolls over and continues to count.
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
CLK Command Address DQ CL= 3 BL= 4
Read Y Q0 Q1 Q2 Q3 Write Y D0 D1 D2 D3
/CAS Latency
Burst Length Burst Type
Burst Length
Initial Address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1
BL Sequential 0 1 2 3 8 4 5 6 7 0 1 4 2 3 0 2 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
0 1 0 1 0 1 0 1 0 1
MITSUBISHI ELECTRIC
15
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
OPERATIONAL DESCRIPTION
BANK ACTIVATE The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A11-0. The minimum activation interval between one bank and the other bank is tRRD.The number of banks which are active concurrently is not limited.
PRECHARGE The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued. Bank Activation and Precharge All (BL=4, CL=3)
CLK
tRCmin
Command A0-9 A10 A11 BA0,1 DQ
ACT tRRD Xa
ACT READ tRAS Xb tRCD Xb Xb 01 00 Qa0 Y 0
PRE tRP
ACT Xb
Xa Xa 00
1
Xb Xb 01
Qa1
Qa2
Qa3
READ
Precharge all
After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A9-0(x4), A8-0(x8), A7-0(X16), and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the autoprecharge (READA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA.
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Multi Bank Interleaving READ (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQ
/CAS latency ACT tRCD Xa Xa Xa 00 00 Y 0 Xb Xb Xb 10 Qa0 10 Qa1 00 Qa2 Qa3 Qb0 Qb1 Qb2 Y 0 0 READ ACT READ PRE
Burst Length
READ with Auto-Precharge (BL=4, CL=3)
CLK
BL + tRP
Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00
READ BL Y 1 tRP
ACT Xa Xa Xa
00 Qa0 Qa1 Qa2 Qa3
00
Internal precharge start
READ Auto-Precharge Timing (BL=4)
CLK Command CL=3 CL=2 DQ DQ
Qa0 ACT READ BL Qa0 Qa1 Qa2 Qa3
Qa1
Qa2
Qa3
Internal Precharge Start Timing
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A9-0 (x 4), A8-0 (x 8) and A7-0 (x 16), and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT) to the same bank is inhib-ited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. The next ACT command can be issued after tRP from the internal precharge timing. The Mode Register can be programmed for burst read and single write. In this mode the write data is only clocked in when the WRITE command is issued and the remaining burst length is ignored. The read data burst length os unaffected while in this mode
Multi Bank Interleaving WRITE (BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00 00 Da0 Y 0 Xb Xb Xb 10 Da1 Da2 Da3 10 Db0 Write ACT tRCD Y 0 0 0 00 Db1 Db2 Db3 0 0 10 Write PRE PRE
WRITE with Auto-Precharge (BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQ
ACT tRCD Xa Xa Xa 00 00 Da0 Da1 Da2 Da3 Internal precharge starts Y 1 Write tWR tRP Xa Xa Xa 00 ACT
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
[ BURST WRITE ] A burst write operation is enabled by setting A9=0 at MRS. A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1,2,4,8, and full-page, like burst read operations.
tRCD
CLK
Command
ACT
WRITE
Address DQ DQ DQ DQ DQ D0 D0 D0 D0 D0 D1 D1 D1 D1 D2 D2 D2 D3 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D9 D10 Dm D0 D1 BL=1 BL=2 BL=4 BL=8 BL=FP
M2V64S20B : m=1023 M2V64S30B : m=511 M2V64S40B : m=255
Full Page counter rolls over and continues to count.
[ SINGLE WRITE ] A single write operation is enabled by setting A9=1 at MRS. In a single write operation, data is written only to the column address specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0.)
CLK Command
ACT tRCD
WRITE
Address
X
Y
DQ
D0
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
BURST INTERRUPTION [ Read Interrupted by Read ] Burst read operation can be interrupted by new read of any bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. Read Interrupted by Read (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQ
00 00 10 Qai0 Qaj0 01 Qaj1 Qbk0 Qbk1 Qbk2 Qal0 Qal1 Qal2 Qal3 READ READ Yi 0 Yj 0 READ Yk 0 READ Yl 0
[ Read Interrupted by Write ] Burst read operation can be interrupted by write of any bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. Read Interrupted by Write (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1
DQM(x4,x8) DQMU/L(x16) 00 00 READ Yi 0 Write Yj 0
Q D
Qai0 Daj0 Daj1 Daj2 Daj3
DQM control Write control
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
[ Read Interrupted by Precharge ] Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is mini-mum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4. Read Interrupted by Precharge (BL=4)
CLK
Command DQ Command
READ
PRE Q0 Q1 Q2
READ
PRE Q0 Q1
CL=3
DQ Command DQ
READ PRE
Q0
Command DQ Command
READ Q0 READ PRE Q0
PRE Q1 Q2
CL=2
DQ Command DQ
READ PRE
Q1
Q0
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
[ Read Interrupted by Burst Terminate ] Similar to a precharge, the burst terminate command, TBST, can interrupt the burst read operation and disable the data output. The READ to TBST interval is a minimum of one CLK. TBST is mainly used to interrupt FP bursts. The figures below show examples, of how the output data is terminated with TBST.
Read Interrupted by Burst Terminate(BL=4)
CLK Command DQ
READ TBST
Q0
Q1
Q2
Q3
CL=3
Command DQ
READ
TBST
Q0
Q1
Q2
Command DQ
READ TBST
Q0
Command DQ
READ
TBST
Q0
Q1
Q2
Q3
CL=2
Command DQ
READ
TBST
Q0
Q1
Q2
Command DQ
READ TBST
Q0
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
[ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=4)
CLK Command A0-9 A10 A11 BA0,1 DQ
00 Dai0 00 Daj0 Daj1 10 00 Dal1 Dal2 Dal3 Write Write Yi 0 Yj 0 Write Yk 0 Write Yl 0
Dbk0 Dbk1 Dbk2 Dal0
[ Write Interrupted by Read ] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care". Write Interrupted by Read (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1
DQM(x4,x8) DQMU/L(x16) 00 00 10 00 Write READ Yi 0 Yj 0 Write Yk 0 READ Yl 0
DQ
Dai0
Qaj0
Qaj1
Dbk0 Dbk1
Qal0
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
[ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Random column access is allowed. Write recovery time (tWR) is required from the last data to PRE command. Write Interrupted by Precharge (BL=4)
CLK Command A0-9 A10 A11 BA0,1
DQM(x4,x8) DQMU/L(x16) 00 00 Write tWR Yi 0 0 PRE tRP Xb Xb Xb 00 ACT
DQ
Dai0
Dai1
Dai2
[ Write Interrupted by Burst Terminate ] A burst terminate command TBST can be used to terminate a burst write operation. In this case, the write recovery time is not required and the bank remains active (Please see the waveforms below). The WRITE to TBST minimum interval is one CLK. Write Interrupted by Burst Terminate(BL=4)
CLK Command A0-9 A10 BA
DQM(x4,x8) DQMU/L(x16) WRITE TBST
Yi
0
0
DQ
Dai0
Dai1
Dai2
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64Mbit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command. Auto-Refresh
CLK /CS NOP or DESELECT /RAS /CAS /WE CKE A0-11 BA0,1
minimum tRC
Auto Refresh on All Banks
Auto Refresh on All Banks
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE (REFSX) for longer than tSRX. After tRC from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh
CLK
Stable CLK
/CS /RAS /CAS /WE CKE
NOP
tSRX
new command X 00
A0-11 BA0,1
Self Refresh Entry
Self Refresh Exit
minimum tRC +1 CLOCK for recovery
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
CLK SUSPEND CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the selfrefresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
ext.CLK
CKE
int.CLK
Power Down by CKE
CLK CKE Command
PRE NOP NOP Standby Power Down
NOP NOP NOP
NOP NOP
CKE Command
ACT NOP NOP
Active Power Down
NOP NOP NOP
NOP NOP
DQ Suspend by CKE
CLK CKE Command
Write READ
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
DQM CONTROL For x4/x8, DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM masks input data word by word. DQM to write mask latency is 0. During reads, DQM forces output to Hi-Z word by word. DQM to output Hi-Z latency is 2. DQM Function
CLK Command DQM
Write READ
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM=H
disabled by DQM=H
For x16, DQMU/L are dual function signals defined as the data mask for writes and the output disable for reads. During writes, DQMU/L mask input data word by word. DQMU/L to write mask latency is 0. During reads, DQMU/L force outputs to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2. DQML and DQMU control lower byte (DQ0-7), and upper byte (DQ8-15), respectively. DQM Function
CLK Command DQML DQMU
Write READ
DQ0-7
D0
D2
D3
Q0
Q1
Q2
Q3
DQ8-15
D0
D1
D2
D3
Q0
Q1
Q3
masked by DQML=H
disabled by DQMU=H
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
ABSOLUTE MAXIMUM RATINGS
Symbol Vdd VddQ VI VO IO Pd Topr Tstg Parameter Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta = 25C Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ Ratings -0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 50 1000 0 - 70 -65 - 150 Unit V V V V mA mW C C
RECOMMENDED OPERATING CONDITIONS
(Ta=0 - 70C, unless otherwise noted )
Limits Symbol Parameter Min. Vdd Vss VddQ VssQ VIH*1 VIL*2 Supply Voltage Supply Voltage Supply Voltage for Output Supply Voltage for Output High-level Input Voltage all inputs Low-level Input Voltage all inputs 3.0 0 3.0 0 2.0 -0.3 Typ. 3.3 0 3.3 0 Max. 3.6 0 3.6 0 VddQ +0.3 0.8 V V V V V V Unit
NOTES) 1. VIH(max)= Vdd+2.0V AC for pulse width less than 3ns acceptable. 2. VIL(min) = -2.0V AC for pulse width less than 3ns acceptable.
CAPACITANCE
(Ta=0 - 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted )
Symbol CI(A) CI(C) CI(K) CI/O Parameter Input Capacitance, address pin Input Capacitance, contorl pin Input Capacitance, CLK pin Input Capacitance, I/O pin 1MHz, 1.4v bias 200mV swing Test Condition Limits (min.) 2.5 2.5 2.5 4.0 Limits (max.) 3.8 3.8 3.5 6.5 Unit pF pF pF pF
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 - 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted )
Limits (max.) -6 120 mA x16 tCLK = 15ns CKE = VIHmin CLK = VILmax (fixed) CKE = VIHmin tCLK = 15ns CKE = VILmax CLK = CKE =VILmax(fixed) CKE = /CS=VIHmin, tCLK=15ns CKE = /CS=VIHmin, CLK=VILmax (fixed) tCLK = 15ns CKE = VILmax CLK = CKE =VILmax(fixed) Icc2N Icc2NS Icc2P Icc2PS Icc3N Icc3NS x4/x8/x16 x4/x8/x16 130 25 20 2 1 55 40 mA mA mA mA mA mA *1,2 *1 *1,2 *1
ITEM
operating current
tRC=min, tCLK =min, BL=1 , CL=3,IOL=0mA single bank operation
Symbol
Organization x4/x8
Unit
Note
Icc1
precharge standby current in Non Power down mode precharge standby current in Power down mode active standby current in Non Power Down Mode active standby current in Power Down Mode
x4/x8/x16 x4/x8/x16 x4/x8/x16 x4/x8/x16
*1 *1,2 *1 *1,2 *1
Icc3P
x4/x8/x16
2 1 145
mA mA
Icc3PS x4/x8/x16 x4/x8 Icc4 x16 Icc5 Icc6 x4/x8/x16 x4/x8/x16
burst current auto-refresh current self-refresh current
All Bank Active,tCLK = min BL=4, CL=3,IOL=0mA
mA 160 150 1 mA mA
*1
tRFC=min, tCLK=min CKE < 0.2V
*1 *1
NOTE) 1. Icc(max) is specified at the output open condition. 2.Input signal are changed one time during 30ns
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 - 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted )
Symbol VOH (DC) VOL (DC) IOZ II Parameter High-Level Output Voltage (DC) Low-level Output Voltage (DC) Off-state Output Current Input Current Test Conditions Min. IOH=-2mA IOL= 2mA Q floating VO=0 -- VddQ VIH = 0 -- VddQ +0.3V -10 -10 2.4 0.4 10 10 Limits Max. V V A A unit
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
AC TIMING REQUIREMENTS
(Ta=0 - 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Input Pulse Levels: 0.8V - 2.0V Input Timing Measurement Level: 1.4V
Limits Symbol Parameter Min. tCLK CLK cycle time CL=3 CL=2 tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tSRX tPDE tREF CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time Input Hold time Row Cycle time Row Refresh Cycle time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Delay time Mode Register Set Cycle time
Self-refresh Exit time Power Down Exit time
-6 Max.
Unit
7.5 10 2.5 2.5 1 1.5 0.8 67.5 75 20 45 20 15 15 15 7.5 7.5 64 100K 10
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
(all inputs) (all inputs)
Refresh Interval time
CLK
1.4V
DQ
1.4V
Any AC timing is referenced to the input signal passing through 1.4V.
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
SWITCHING CHARACTERISTICS
(Ta=0 - 70C, Vdd= VddQ= 3.3 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Limits Symbol Parameter Min. tAC Access time from CLK CL=3 CL=2 tOH Output Hold time from CLK Delay time, output lowimpedance from CLK Delay time, output highimpedance from CLK CL=3 CL=2 2.7 3.0 0 2.7 5.4 -6 Max. 5.4 6.0 ns ns ns ns ns ns *1 Unit Note
tOLZ tOHZ
NOTE) 1. If clock rising time is longer than 1ns, (tr /2-0.5ns) should be added to the parameter.
Output Load Condition
VOUT Ext.CL=50pF
CLK
1.4V
DQ
1.4V
Output Timing Measurement Reference Point
CLK tOLZ DQ
1.4V
1.4V
tAC
tOH
tOHZ
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Burst Write (single bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE
tWR
CKE
DQM(U/L)
A0-9 * A10 A11
X
Y
X
Y
X
X
X
X
BA0,1 DQ
0
0
0
0
0
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT#0
WRITE#0
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
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PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS /RAS
tRRD
tRRD
tRAS
tRP
tRCD
tRCD
/CAS /WE
tWR tWR
CKE
DQM(U/L)
A0-9 * A10 A11
X
X
Y
Y
X
X
Y
X
X
X
X
X
X
X
X
BA0,1 DQ
0
1
0
1
0
0
1
2
0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1
ACT#0
ACT#2 WRITE#0 PRE#1
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
34
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Burst Read (single bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS /WE CKE
DQM(U/L) DQM read latency =2
A0-9 * A10 A11
X
Y
X
Y
X
X
X
X
BA0,1 DQ
0
0
0
0
0
CL=3
Q0 Q0 Q0 Q0 Q0 Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
READ to PRE BL allows full data out
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
35
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Burst Read (multiple bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS /RAS
tRRD tRAS tRP
tRRD
tRCD
tRCD
/CAS /WE CKE
DQM(U/L) DQM read latency =2
A0-9 * A10 A11
X
X
Y
Y
X
X
Y
X
X
X
X
X
X
X
X
BA0,1 DQ
0
1
0
1
0
0
1
2
0
CL=3
Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1 Q0
ACT#0
READ#0 ACT#1
PRE#0 READ#1
ACT#0 PRE#1
READ#0 ACT#2
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
36
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Burst Write (multi bank) with Auto-Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD tRCD
/CAS
BL-1+ tWR + tRP BL-1+ tWR + tRP
/WE CKE
DQM(U/L)
A0-9 * A10 A11
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
BA0,1 DQ
0
1
0
1
0
0
1
1
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
D1
ACT#0 ACT#1
WRITE#0 with AutoPrecharge
ACT#0 WRITE#1 with AutoPrecharge
WRITE#0 ACT#1 WRITE#1
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
37
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Burst Read (multiple bank) with Auto-Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
tRC
/CS
tRRD tRRD
/RAS
tRCD tRCD tRCD
/CAS
BL+tRP BL+tRP
/WE CKE
DQM(U/L) DQM read latency =2
A0-9 * A10 A11
X
X
Y
Y
X
Y
X
Y
X
X
X
X
X
X
X
X
BA0,1 DQ
0
1
0
1
0
0
1
1
CL=3
Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
CL=3
Q0 Q0
ACT#0 ACT#1
READ#0 with Auto-Precharge
ACT#0 READ#1 with Auto-Precharge
READ#0 ACT#1
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
38
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Page Mode Burst Write (multi bank) @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE
DQM(U/L)
A0-9 * A10 A11
X
X
Y
Y
Y
Y
X
X
X
X
BA0,1 DQ
0
1
0
0
1
0
D0
D0
D0
D0
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
ACT#0
WRITE#0 ACT#1
WRITE#0 WRITE#1
WRITE#0
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
39
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Page Mode Burst Read (multi bank) @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE
DQM(U/L) DQM read latency=2
A0-9 * A10 A11
X
X
Y
Y
Y
Y
X
X
X
X
BA0,1 DQ
0
1
0
0
1
0
CL=3
Q0 Q0
CL=3
Q0 Q0 Q0 Q0
CL=3
Q0 Q0 Q1 Q1 Q1 Q1
ACT#0
READ#0 ACT#1
READ#0 READ#1
READ#0
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
40
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Write Interrupted by Write / Read @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD tCCD
/CAS /WE CKE
DQM(U/L)
A0-9 * A10 A11
X
X
Y
Y
Y
Y
Y
X
X
X
X
BA0,1 DQ
0
1
0
0
0
1
0
CL=3
D0 D0 D0 D0 D0 D0 D1 D1 Q0 Q0 Q0 Q0
ACT#0
WRITE#0 WRITE#0 WRITE#0 READ#0 ACT#1 WRITE#1
Burst Write can be interrupted by Write or Read of any active bank. Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
41
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Read Interrupted by Read / Write @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE
DQM(U/L) DQM read latency=2
A0-9 * A10 A11
X
X
Y
Y
Y
Y
Y
Y
X
X
X
X
BA0,1 DQ
0
1
0
0
0
1
0
0
Q0
Q0
Q0
Q0
Q0
Q0
Q1
Q1
Q0
D0
D0
ACT#0
READ#0 READ#0 READ#0 READ#0 WRITE#0 ACT#1 READ#1 blank to prevent bus contention
Burst Read can be interrupted by Read or Write of any active bank. Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
42
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Write Interrupted by Precharge @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD
/RAS
tRCD
/CAS /WE CKE
DQM(U/L)
A0-9 * A10 A11
X
X
Y
Y
X
Y
X
X
X
X
X
X
BA0,1 DQ
0
1
0
1
0
1
1
1
D0
D0
D0
D0
D1
D1
D1
D1
D1
ACT#0
WRITE#0 ACT#1
PRE#0 WRITE#1 PRE#1
ACT#1
WRITE#1
Burst Write is not interrupted by Precharge of the other bank.
Burst Write is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
43
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Read Interrupted by Precharge @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRRD tRP
/RAS
tRCD tRCD
/CAS /WE CKE
DQM(U/L) DQM read latency=2
A0-9 * A10 A11
X
X
Y
Y
X
Y
X
X
X
X
X
X
BA0,1 DQ
0
1
0
1
0
1
1
1
Q0
Q0
Q0
Q0
Q1
Q1
ACT#0
READ#0 ACT#1
PRE#0 READ#1 PRE#1
ACT#1
READ#1
Burst Read is not interrupted by Precharge of the other bank.
Burst Read is interrupted by Precharge of the same bank. Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
44
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Mode Register Setting
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRC
tRSC
/RAS
tRCD
/CAS /WE CKE
DQM(U/L)
A0-9 * A10 A11
M
X
Y
X
X
BA0,1 DQ
Auto-Ref (last of 8 cycles)
0
0
0
D0
D0
D0
D0
Mode Register Setting
ACT#0
WRITE#0
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
45
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Auto-Refresh @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS
tRC
/RAS
tRCD
/CAS /WE CKE
DQM(U/L)
A0-9 * A10 A11
X
Y
X
X
BA0,1 DQ
Auto-Refresh Before Auto-Refresh, all banks must be idle state.
0
0
D0
D0
D0
D0
ACT#0
WRITE#0
After tRC from Auto-Refresh, all banks are idle state. Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
46
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Self-Refresh
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK
CLK can be stopped tRC+1
/CS /RAS /CAS /WE
tSRX
CKE
CKE must be low to maintain Self-Refresh DQM(U/L)
A0-9 * A10 A11
X
X
X
BA0,1 DQ
Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state. Self-Refresh Exit After tRC from Self-Refresh Exit, all banks are idle state.
0
ACT#0
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
47
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
DQM Write Mask @BL=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
DQM(U/L)
A0-9 * A10 A11
X
Y
Y
Y
X
X
BA0,1 DQ
0
0
0
0
masked
D0 D0 D0 D0 D0 D0 D0
masked
ACT#0
WRITE#0
WRITE#0
WRITE#0
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
48
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
DQM Read Mask @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
DQM(U/L)
DQM read latency=2
A0-9 * A10 A11
X
Y
Y
Y
X
X
BA0,1 DQ
0
0
0
0
masked
Q0 Q0 Q0 Q0
masked
Q0 Q0 Q0
ACT#0
READ#0
READ#0
READ#0
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
49
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Power Down
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS /CAS /WE
Standby Power Down Active Power Down
CKE
CKE latency=1 DQM(U/L)
A0-9 * A10 A11
X
X
X
BA0,1 DQ
Precharge All
0
ACT#0
Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
50
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
CLK Suspend @BL=4 CL=3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
CLK /CS /RAS
tRCD
/CAS /WE CKE
CKE latency=1 DQM(U/L) CKE latency=1
A0-9 * A10 A11
X
Y
Y
X
X
BA0,1 DQ
0
0
0
D0
D0
D0
D0
Q0
Q0
Q0
Q0
ACT#0
WRITE#0 CLK suspended
READ#0 CLK suspended Italic parameter indicates minimum case
* A9 (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
51
PC133 SDRAM (Rev.0.5) Oct. '99
64M bit Synchronous DRAM
M2V64S20BTP-6 (4-BANK x 4194304-WORD x 4-BIT) M2V64S30BTP-6 (4-BANK x 2097152-WORD x 8-BIT) M2V64S40BTP-6 (4-BANK x 1048576-WORD x 16-BIT)
MITSUBISHI LSIs
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable,but there is always the possibility that trouble may occur with them. Trouble with semiconductors consideration to safety when making your circuit designs,with appropriate measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application;they do not convey any license under any intellectual property rights,or any other rights,belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights,originating in the use of any product data,diagrams,charts or circuit application examples contained in these materials. 3.All information contained in these materials,including product data, diagrams and DQM(U/L) charts,represent information on products at the time of publication of these materials,and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric A0-9 * Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.
A10
4.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product A11 distributor when considering the use of a product contained herein for special applications,such as apparatus or systems for transportation, vehicular, medical,aerospace,nuclear,or undersea repeater use. 5.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 6.If these products or technologies are subject the Japanese export control restrictions,they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor * A9 product distributor for further details on these materials or the products contained therein. (x8) and A8,A9 (x16) for column address of read/write are don't care
MITSUBISHI ELECTRIC
52

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